msm_serial_hsl_probe: detected port #0 (ttyMSM0) Serial: 8250/16550 driver, 2 ports, IRQ sharing disabled tcsr 1953000.ess_tcsr: setting ess interface select = 0 tcsr 194b000.tcsr: setting usb hs phy mode select = e700e7 io scheduler deadline registered (default) jffs2: version 2.2 (NAND) (SUMMARY) (LZMA) (RTIME) (CMODE_PRIORITY) (c) 2001-2006 Red Hat, Inc. squashfs: version 4.0 (1) Phillip Lougher futex hash table entries: 1024 (order: 4, 65536 bytes)

hw perfevents: enabled with ARMv7 Cortex-A7 PMU driver, 5 counters available UDP-Lite hash table entries: 256 (order: 1, 8192 bytes) UDP hash table entries: 256 (order: 1, 8192 bytes) TCP: Hash tables configured (established 2048 bind 2048) TCP bind hash table entries: 2048 (order: 2, 16384 bytes) TCP established hash table entries: 2048 (order: 1, 8192 bytes) Switched to clocksource arch_sys_counter

msm_bus_device 580000.ad-hoc-bus: Failed to get bus clk for bus1024 ctx1 msm_bus_device 580000.ad-hoc-bus: Failed to get bus clk for bus4096 ctx1 msm_bus_device 580000.ad-hoc-bus: Vrail-comp is missing, default to 100 msm_bus_device 580000.ad-hoc-bus: Util-fact is missing, default to 100 hw-breakpoint: Debug register access (0xee003e17) caused undefined instruction on CPU 0 hw-breakpoint: CPU 2 failed to disable vector catch hw-breakpoint: Debug register access (0xee003e17) caused undefined instruction on CPU 1 hw-breakpoint: Debug register access (0xee003e17) caused undefined instruction on CPU 2 hw-breakpoint: Debug register access (0xee003e17) caused undefined instruction on CPU 3 DMA: preallocated 2048 KiB pool for atomic coherent allocations pinctrl core: initialized pinctrl subsystem VFP support v0.3: implementor 41 architecture 2 part 30 variant 7 rev 5 SMP: Total of 4 processors activated (384.00 BogoMIPS). Setting up static identity map for 0x80213768 - 0x802137c0 Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes) Mount-cache hash table entries: 1024 (order: 0, 4096 bytes) Calibrating delay loop (skipped), value calculated using timer frequency. sched_clock: 56 bits at 48MHz, resolution 20ns, wraps every 2863311552512ns Architected cp15 timer(s) running at 48.00MHz (virt). Preemptible hierarchical RCU implementation. SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1 Inode-cache hash table entries: 16384 (order: 4, 65536 bytes) Dentry cache hash table entries: 32768 (order: 5, 131072 bytes) PID hash table entries: 1024 (order: 0, 4096 bytes) Kernel command line: init=/sbin/init rootfstype=squashfs ubi.mtd=13,2048 ubi.block=0,0 root=/dev/ubiblock0_0 rootwait ro clk_ignore_unused

Built 1 zonelists in Zone order, mobility grouping on. Reserved memory: failed to reserve memory for node base 0x87000000, size 5 MiB Machine model: Linksys EA6350v3 based on Qualcomm Technologies, Inc. CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache

CPU: ARMv7 Processor revision 5 (ARMv7), cr=10c5387d

Linksys router firmware update